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Understanding the Cell Microprocessor

 by Anand Lal Shimpi on March 17, 2005 12:05 AM EST
70 Comments | Add A Comment
70 Comments

Understanding Gates

The fundamental building blocks of any microprocessor are gates.  Gates are collections of transistors that electrically mimic a particular logic function.   For example, a 2-input AND gate will take two input signals and output a 1 only if the two inputs are both 1s.   An XOR gate will output a 1 only if the two inputs are different.   A NOR gate will output a 1 only if all inputs are 0s.

Combinations of these gates are used to implement everything in a microprocessor, including functional units like adders, multipliers, etc.


Here, we have a 1-bit carry adder implemented using logic gates.  It will add any two 1-bit numbers and produce a result.

However, there are many ways to implement each gate, as long as the behavior of the gate remains the same independent of the implementation.   It’s just like doing a math problem; there are multiple ways to find the solution - some just may be more efficient than others.

A very popular way of designing gate logic is using what is known as static CMOS.   Static CMOS designs are relatively easy to implement and there are tons of libraries available for automated (e.g. computer driven) static CMOS design.   There are a couple of problems with static CMOS design:
  1. Static CMOS circuits aren’t the fastest circuits possible, which is why they aren’t used in things like Intel’s double-pumped ALUs where high clock speeds are necessary.
  2. Static CMOS designs use quite a few transistors.   For each m-input gate, you need 2 * m transistors (m PMOS and m NMOS transistors), which for high fan-in gates (gates with lots of inputs), it drives transistor counts up considerably.   As is the case with any heavily SIMD architecture, high fan-in gates are commonplace.
Let’s take a look at a static CMOS NOR gate:

First thing to note is that for every NMOS transistor we add, there’s a complementary PMOS transistor.   With each additional input to the NOR gate, we have to add two transistors - one PMOS and one NMOS - hence the 2*m transistors from before.

There’s another problem here - the NOR gate isn’t clocked.   Normally, large collections of gates are assembled and put behind an element called a latch, which is clocked.   One type of large collection would be all of the circuitry used for a pipeline stage.   This isn’t really a problem for static CMOS gates, as it greatly simplifies the distribution of clocks to the chip (since you don’t have to route a clock signal to every gate, just every latch, and there are far more general gates than there are latches).

Designing and implementing static CMOS gates are extremely easy.   Hardware Description Languages (HDLs), programming languages in which chips are “written” have widespread static CMOS libraries, meaning that a chip designer can focus on writing code to crank out a chip without having to hand design its circuits.   But as success is usually proportional to difficulty, static CMOS designs aren’t the fastest things in the world.   Things like Intel’s 7.2GHz ALUs aren’t designed using static CMOS logic, neither is Cell.

Manufacturing, Die Size and Clock Speed Cell's Dynamic Logic
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  • WishIKnewComputers - Thursday, March 17, 2005 - link

    Well, I dont really see the Cell 'breaking' in any way. Between being in the PS3, IBM servers/supercomputers, and Sony and Toshiba electronics, the chip will be all over the place.

    As for it showing up in PCs... no it wont happen anytime soon, but I really dont think it's intended to at this point. Workstation and playstations are its main concern, and smartly so. The Cell in its first generation isnt cut out for superior general tasking, obviously, but when those things start pumping out (and they will... the PS2 has sold what, 80 million units?), there will likely be different and more advanced versions. And if some of those are changed for enhanced general purposing somehow or another, then they could have shot at entering the PC world. As for taking on Intel, though... I dont think IBM is even considering that. If I had to guess, if they wanted to be in a PC, they would have OS X adapted to Cell and IBM would have these things in Apples.

    But no matter which way they go, is it me or does IBM seem light-years ahead of Intel? After looking at Intel's future plans, it seems that they are trying to move towards what IBM is doing now. So is the Cell a processor just ahead of its time, or has Intel just gotten behind?

  • AnnihilatorX - Thursday, March 17, 2005 - link

    This article is seriously a kill for a child like me. I appreciate it though. Well done Anandtech

  • ravedave - Thursday, March 17, 2005 - link

    I can't wait to see what devlopers thing of the cell & the SDK's for it. I have a feeling thats what will kill the cell or make it successfull.

  • microbrew - Thursday, March 17, 2005 - link

    "System on a Chip (SoC)"

    What will make or break the Cell is the tools available, especially the operating system and libraries.

    I would like to see what they're doing in terms of marketing the chip to consumer electronics, telecom, military and other embedded applications. I could see the Cell as a viable alternative to the usual mixures of PowerPcs, ARMs and DSPs.

    I also agree with Final Words; I don't see the Cell breaking into the consumer PC market any time soon either.

  • Locut0s - Thursday, March 17, 2005 - link

    #17 Yeah that was a bit too harsh I agree.

  • Eug - Thursday, March 17, 2005 - link

    I'm just wondering how well a dual-core PPE-based 4+ GHz chip would do in general purpose (desktop) code.

    And I also wonder how cool/hot such a chip would be. The Xbox 2's CPU is probably a 3-core PPE, but it runs at 3 GHz, and we don't have power specs for it anyway.

  • Filibuster - Thursday, March 17, 2005 - link

    #11 (well, everyone should if they haven't before) read the Arstechnica article on PS2 vs PC - static applications vs dynamic media. Cell is taking it to the next level.

    http://arstechnica.com/articles/paedia/cpu/ps2vspc...

    Very nice article Anand!

  • Googer - Thursday, March 17, 2005 - link

    Besides a release date, is there any news or knowledge of a Linux Kit for Playstation 3 like there was for PS2? Does anyone KNOW OF Either?

  • Illissius - Thursday, March 17, 2005 - link

    Damn. Awesome article. If I hadn't known the site and author beforehand, I would've guessed Ars and Hannibal. Seems he isn't the only one with a talent for these kinds of articles ;)
    You should do more of them.

  • scrotemaninov - Thursday, March 17, 2005 - link

    #22: This is just a guess so don't rely on this. The POWER5 has 2way SMT. Each cycle it fetches 8 instructions from the L1I cache. All instructions fetched per cycle are for the same thread so it alternates (round robin). It also has capabilities for setting the thread priority so that you effectively run with 1 thread and it just fetches 8 instructions per cycle for the one running thread.

    I would expect the PPE to be similar to this, fetching 2 instructions for the same thread each cycle. The POWER5 has load balancing stuff in there too - if one thread keeps missing in L2 then the other thread gets more instructions decoded in order to keep the CPU functional unit utilisation up. I've no idea whether this kind of stuff has made it over into the PPE, I'd be a little surprised if it has, especially seeing as this is in-order anyway so it's not like you're going to be aiming for high utilisations rates.
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