Understanding the Cell Microprocessor
by Anand Lal Shimpi on March 17, 2005 12:05 AM EST- Posted in
- CPUs
Blueprint for a High Performance per Transistor CPU
Given that Cell was designed with a high performance per transistor metric in mind, its architecture does serve as somewhat of a blueprint for the technologies that result in the biggest performance gains, at the lowest transistor counts. Now that we’ve gone through a lot of the Cell architecture, let’s take a look back at what some of those architectural decisions are:1. On-die memory controller
We’ve seen this with the Athlon 64, but an on-die memory controller appears to be one of the best ways to improve overall performance, at minimal transistor expenditure. Furthermore, we also see the use of Rambus’ XDR memory instead of conventional DDR, as the memory of choice for Cell. High frequencies and high bandwidth are what Cell thrives on, and for that, there’s no substitute but Rambus’ technology.
2. SMT
On-die multithreading has also been proven to be a good way of extracting performance at minimal transistor impact. Introducing Hyper Threading to the Pentium 4’s core required a die increase of less than 5%, just to give you an idea of the scale of things. The performance benefits to SMT will obviously vary depending on the architecture of the CPU. In the case of the Pentium 4, performance gains ranged from 0 - 20%. In the case of the in-order PPE core of Cell, the performance gains could be even more. Needless to say, if implemented well, and if proper OS/software support is there, SMT is a feature that makes sense and doesn’t strain the transistor budget.
3. Simpler, in-order, narrow-issue core - but lots of them
This next design decision is more controversial than the first two, simply because it goes against the design strategies of most current generation desktop microprocessors that we’re familiar with. By making the PPE and SPEs 2-issue only, each individual core still remains a manageable size. Narrower cores obviously sacrifice the ability to extract ILP, but doing so allows you to cram more cores onto a single die - highlighting the ILP for TLP sacrifice that the Cell architects have made.
Getting rid of the additional logic and windows needed for an out-of-order core helps further reduce transistor count, but at the expense of making sure that you have a solid compiler and/or developers that are willing to deal with more of the architecture’s intricacies to achieve good performance.
Looking at Intel’s roadmap for Platform 2015, the type of microprocessors that they’re talking about are eerily Cell-like - a handful of strong general purpose cores surrounded by smaller cores, some of which are more specialized hardware.
Facebook
Twitter
RSS
70 Comments
View All Comments
faboloso112 - Thursday, March 17, 2005 - link
ahh i love bedtime stories!great read...VERY informative!
ksherman - Thursday, March 17, 2005 - link
sweet article! way over my head, but there were some parts that were dropped down to my level of understanding. Leave it to anand to tell the real story. It will be interesting to see how willing some companies will be to accomidate Sony's ratical processor... bu tas long as theirs money... Do you think that it is possible to (down the road) flop a x86 chip in place of the PPE? wouldn't hat make the Cell compatible with the current processing standards?ProviaFan - Thursday, March 17, 2005 - link
Describing this as a "sit down read" type of article makes me want to print it out to put it in the magazine rack, because I don't have a laptop + 802.11g to peruse AnandTech while I'm, er... ;)xsilver - Thursday, March 17, 2005 - link
nice, definitley one of those "sit down reads".... some serious shiznit ;)cosmotic - Thursday, March 17, 2005 - link
OMG! FIRST POST LOL ROFL LMAO OMG!!! LOOK WHOS COOL!!!Fricardo - Thursday, March 17, 2005 - link
Finally! Thanks guys.Bawl - Saturday, January 25, 2014 - link
I just love this deep analysis of one of the most mist-understanding processor of the last decade.Too bad that after spending more than a half-of-billion dollars, SonyThoshibaIBM didn't release the presumably outstanding CellTwo.
Ferrx - Sunday, December 20, 2015 - link
Hi, can you help me to understand this ? I don't understand at all about these._______ _________ ______
|Decode| | Execute | | Write |
----------- ---------------- -----------
| I1 | I2 | | | | | | | |
| I3 | I4 | | I1 | I2 | | | | |
| I3 | I4 | | I1 | | | | I2 | |
| | I4 | | | | | | I1 | I3 |
| I5 | I6 | | | | I4 | | I4 | |
| | I6 | | | I5 | | | I5 | |
| | | | | I6 | | | I6 | |
_______ _________ ______
In "Decode", each row has 2 columns. What do First and Second Column mean ?
same as "Write"
And in "Execute, each row has 3 columns. What do First, Second and Third column mean ?
And how is the process ? (The current table is about "In-Order Issue with Out-of-Order Completion").
I've read it many times, in the "Instruction Level Parallelism". But I still don't have any idea about it.
Ferrx - Sunday, December 20, 2015 - link
Hi, can you help me to understand this ? I don't understand at all about these._______ _________ ______
|Decode| | Execute | | Write |
----------- ---------------- -----------
| I1 | I2 | | | | | | | |
| I3 | I4 | | I1 | I2 | | | | |
| I3 | I4 | | I1 | | | | I2 | |
| | I4 | | | | | | I1 | I3 |
| I5 | I6 | | | | I4 | | I4 | |
| | I6 | | | I5 | | | I5 | |
| | | | | I6 | | | I6 | |
_______ _________ ______
In "Decode", each row has 2 columns. What do First and Second Column mean ?
same as "Write"
And in "Execute, each row has 3 columns. What do First, Second and Third column mean ?
And how is the process ? (The current table is about "In-Order Issue with Out-of-Order Completion").
I've read it many times, in the "Instruction Level Parallelism". But I still don't have any idea about it.
Ferrx - Sunday, December 20, 2015 - link
Aww... Can't do tab-'ing' 0__0