PCI Express 2.0: Scalable Interconnect Technology, TNG

Final Thoughts

As we have seen, PCI Express 2.0 is the next step in the quest for more bandwidth. This trend has been around since the beginning of time as each successive generation usually doubles the maximum bandwidth of the previous generation (or technology). This only makes sense as according to Moore's Law the number of transistors placed in an inexpensive integrated circuit approximately doubles every two years - improvements in interconnect technology necessary to support these advancement are the logical extension of this law. Looking for performance improvements in today's technology offerings with the next-generation interconnect technology (like PCI Express 2.0) is largely futile. The real benefit may come in the next round of video card releases - or perhaps Generation Next^2. Still, those that are quick to brush off PCI Express 2.0 as ineffective and unimportant should recall the past. The difference in performance experienced during the transition from AGP to PCI Express 1.x was not necessarily a revolution at the time, but there are benefits to using PCI-E instead of the aging PCI interface, and we may see new implementations of PCI-E technology that make the 2.0 revision more important.

Just about every interconnect technology is moving from high-pin count parallel interfaces to high-speed, low-pin count, serial, point-to-point interfaces. We have seen the incredible difference moving to a low-latency, high-bandwidth interfaces made in the transition from PATA to SATA as well as PCI/AGP to PCI Express (AGP was really just a kludged-together remake of PCI technology). Moreover, we will see it again in the near future when Intel leaves behind their antiquated FSB topology for QuickPath - something AMD did years ago with the release of their Opteron/Athlon 64 line featuring HyperTransport Technology. Removing the MCH altogether means moving the memory controller on die as well as relocating PCI Express resources to the CPU. The X38/X48 chipset will simultaneously be the first and last Intel MCH to make use of PCI Express 2.0 technology. (Unless the fabled P45 chipset, the 65nm die-shrink of P35 with additional improvements, see's the light of day.)

No doubt, those that run their systems with PCI Express 2.0 graphics cards installed will see an increase in MCH power consumption. Although we can't tell you exactly what share of the consumption figure is due to PCI Express circuit operation, what we can tell you is that it went up - those portions of the die that must run at the base link frequency of 5.0GHz have at least doubled from the days of PCI Express 1.x. What this means to the bottom line we don't know - perhaps this can help us explain why X38 seems to be so darn hot at times.

Maybe in the future we will see a mechanism that allows us to force PCI Express 1.x operation with PCI Express 2.0 capable graphics cards on some motherboards. (We do not recall testing many boards that had this option - allowing for PCI Express 1.1 or 1.0a.) This would be the only way for us to determine if the increased signaling rate makes a big a difference for today's products, but while we would hope it helps we remain skeptical at best. Purchasing a PCI Express 2.0 graphics cards at this time is future proofing more than anything else; we haven't noticed any performance differences when comparing PCI-E 1.x chipsets to PCI-E 2.0 chipsets with the newer GPUs, and we don't expect you to either. PCI-E 2.0 may prove more useful as a way to provide four x8 slots that each offer the same bandwidth as the older 1.x x16 slots. With Triple-SLI, Tri-Fire, and talk of GPU physics accelerators, including additional high-bandwidth slots on motherboards makes sense.