Barcelona Architecture: AMD on the Counterattack
by Anand Lal Shimpi on March 1, 2007 12:05 AM EST- Posted in
- CPUs
Core Tune-up
While the most significant sounding improvements were rolled into the SSE128 changes in Barcelona, they are merely the tip of the iceberg. The laundry list of improvements to Barcelona starts with the branch predictor.
In general, the accuracy of a CPU's branch predictor determines how wide and how deep of a design you can make. The average number of instructions before the predictor mispredicts governs how many instructions you can have in flight, which in turn controls how many execution units you can realistically keep fed on a regular basis. The K8's branch predictor was quite good and very well optimized for its architecture, but there were some advancements Intel introduced in the Pentium M and Pentium 4 that AMD could stand to benefit from.
Barcelona adds a 512-entry indirect predictor which, believe it or not, predicts indirect branches. An indirect branch is one where the target of the branch is a location pointed to by an address in memory, in other words, a branch with multiple targets. Instead of branching directly to a label indicated by the branch instruction, an indirect branch sends the CPU to a memory location that contains the location of the instruction that it should branch to.
Intel added an indirect predictor to its Pentium M processor based on the idea that the more you could limit the number of mispredicted branches, the more efficient your processor could be (thus lowering power consumption). The indirect predictor also made its way into Prescott in order to help minimize the performance deficit incurred by further pipelining the NetBurst architecture.
In Prescott, the simple addition of an indirect predictor resulted in over a 12% reduction in mispredicted branches in SPEC CPU2000. While details of how AMD and Intel differ in their predictor algorithms aren't public, we can expect similarly large improvements in areas where indirect branches are common. In the 253.perlbmk test of SPEC CPU2000 the reduction in mispredicted branches with Prescott was significant, reaching almost 55%. With Barcelona, fewer mispredicted branches means higher overall IPC and greater efficiency both from a power and performance standpoint. AMD doesn't have the incredibly deep pipeline to worry about that Intel did with Prescott, but the efficiency improvements should be significant.
The inclusion of an indirect predictor wasn't the only crystal ball improvement in Barcelona; the size of the return stack in the new core is double what it was in K8. In very deep call chains, for example code that calls many subroutines (e.g. recursive functions), the CPU will eventually run out of room to keep track of where it has been. Once it starts losing track of return addresses, it loses the ability to predict branches involved with those addresses. Barcelona helps alleviate the problem by doubling the size of the return stack. These sorts of improvements are generally implemented by profiling the behavior of software commonly used on a manufacturer's CPU, so we asked AMD what software or scenario drove this improvement of Barcelona. AMD wouldn't give us a concrete example of a situation other than to say that the return stack size improvements were made at the request of a "large software vendor".
The final improvement to the K8's branch prediction came through the usual channels - Barcelona now tracks more branches than its predecessor. There's no mystic science to branch prediction; a processor simply looks at branches it has taken and bases its predictions on historical data. The more historical data that is present, the more accurate a branch predictor becomes. When the K8 was designed it was built on a 130nm manufacturing process; with the first incarnation of Barcelona set to debut at 65nm AMD definitely has the die space to track more branch history data.
While the most significant sounding improvements were rolled into the SSE128 changes in Barcelona, they are merely the tip of the iceberg. The laundry list of improvements to Barcelona starts with the branch predictor.
In general, the accuracy of a CPU's branch predictor determines how wide and how deep of a design you can make. The average number of instructions before the predictor mispredicts governs how many instructions you can have in flight, which in turn controls how many execution units you can realistically keep fed on a regular basis. The K8's branch predictor was quite good and very well optimized for its architecture, but there were some advancements Intel introduced in the Pentium M and Pentium 4 that AMD could stand to benefit from.
Barcelona adds a 512-entry indirect predictor which, believe it or not, predicts indirect branches. An indirect branch is one where the target of the branch is a location pointed to by an address in memory, in other words, a branch with multiple targets. Instead of branching directly to a label indicated by the branch instruction, an indirect branch sends the CPU to a memory location that contains the location of the instruction that it should branch to.
Intel added an indirect predictor to its Pentium M processor based on the idea that the more you could limit the number of mispredicted branches, the more efficient your processor could be (thus lowering power consumption). The indirect predictor also made its way into Prescott in order to help minimize the performance deficit incurred by further pipelining the NetBurst architecture.
In Prescott, the simple addition of an indirect predictor resulted in over a 12% reduction in mispredicted branches in SPEC CPU2000. While details of how AMD and Intel differ in their predictor algorithms aren't public, we can expect similarly large improvements in areas where indirect branches are common. In the 253.perlbmk test of SPEC CPU2000 the reduction in mispredicted branches with Prescott was significant, reaching almost 55%. With Barcelona, fewer mispredicted branches means higher overall IPC and greater efficiency both from a power and performance standpoint. AMD doesn't have the incredibly deep pipeline to worry about that Intel did with Prescott, but the efficiency improvements should be significant.
The inclusion of an indirect predictor wasn't the only crystal ball improvement in Barcelona; the size of the return stack in the new core is double what it was in K8. In very deep call chains, for example code that calls many subroutines (e.g. recursive functions), the CPU will eventually run out of room to keep track of where it has been. Once it starts losing track of return addresses, it loses the ability to predict branches involved with those addresses. Barcelona helps alleviate the problem by doubling the size of the return stack. These sorts of improvements are generally implemented by profiling the behavior of software commonly used on a manufacturer's CPU, so we asked AMD what software or scenario drove this improvement of Barcelona. AMD wouldn't give us a concrete example of a situation other than to say that the return stack size improvements were made at the request of a "large software vendor".
The final improvement to the K8's branch prediction came through the usual channels - Barcelona now tracks more branches than its predecessor. There's no mystic science to branch prediction; a processor simply looks at branches it has taken and bases its predictions on historical data. The more historical data that is present, the more accurate a branch predictor becomes. When the K8 was designed it was built on a 130nm manufacturing process; with the first incarnation of Barcelona set to debut at 65nm AMD definitely has the die space to track more branch history data.
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Amiteriver - Tuesday, March 27, 2007 - link
Sounds groooovyNow lets just hope they have something good to plug it into.
trisweb2 - Friday, March 16, 2007 - link
I just want to say how refreshing it is to read an article written by Anand. He is a master of the English language; he perfectly communicates and explains every technical detail and I come away with a better understanding of whatever he's talking about.Thank you, Anand, for being a good writer!
MrWizard6600 - Thursday, March 22, 2007 - link
I Agree, Outstanding.No other site I know of gives nearly as many in depth details, and while ill admit my knowlage of some of the terms is sketchy, I got through that one with a good understanding.
Sounds like AMD has something to fight Core 2 against.
I do have one criticism:
I would have loved to have heard what Intels equivilent to all of AMDs technologies would be, mind you this criticism corrects it self toward the end of the artical.
stance - Monday, March 5, 2007 - link
Remember AMD's old president and CEO Jerry Sanders with commentslike "We will see what we see" and "More bang for your buck" I
cannot wait to see duel socket motherboards with two four core
Barcelona's working their magic. reminds me of Carol shelby
when he brought the Cobra out for road test. exciting is not
the word, jaw droping performance? Don't take Richard's Statements
lightly
lordsnow - Sunday, March 4, 2007 - link
Does anyone have any idea how compatible the "Barcelona" CPU will be with current motherboards? When it comes out, does it need a new n-phase voltage regulator, for example?the reason I'm asking is, I want to upgrade and with the current state of affairs was going to go for a C2D CPU. But with these Barcelona CPU's due out I may stick with AMD - get a AM2 motherboard and cheap AM2 CPU and upgrade to the Barcelona CPU at a later date. But I have to be sure that whatever motherboard I buy now will be 100% Barcelona compatible.
Can anyone inform us about what the situation is in this regard?
coldpower27 - Sunday, March 4, 2007 - link
Barcelona being the server variant will be compatible with the Socket F infrastructure, while Agena will be a Socket AM2+ processor compatible with exisiting Socket AM2 infrastructure.lordsnow - Sunday, March 4, 2007 - link
Any ideas as to what kind of features a user will be missing by dropping a AM2+ "Agena" CPU into a AM2 socket? The enhanced Power Saving features, perhaps?chucky2 - Sunday, March 4, 2007 - link
I asked above and non-AnandTech folks like you and I said it would...but no one from AnandTech themselves jumped right in to give an affirmative.I asked for links from AMD's own website confirming that Agena and Kuma would work in current AM2 motherboards, and no one posted back.
Right now the AM2+ CPU's will work in current AM2 boards rumor is just that, a rumor...when AMD themselves confirm it, or a site such as AnandTech confirms it with AMD and reports on it, then I'll believe it.
Until then, it's <i>probable</i> that AM2+ will work in current AM2 motherboards...if you're willing to take the risk I say go for it, else, wait until we have an official answer one way or the other.
JMHO...
Chuck
Calin - Saturday, March 3, 2007 - link
"Intel regained the undisputed performance crown it hadn't seen ever since the debut of AMD's Athlon 64."Intel in fact lost the "undisputed performance king" title during the early lifetime of the K7 architecture. The Pentium !!! was faster at some tasks and slower at others (games) than the K7. Before that, the Pentium II was better than the K6-2 (the K6-3 had better IPC than Pentium3, but was slower in MHz)
coldpower27 - Sunday, March 4, 2007 - link
Intel had the undisputed performance crown again with the Athlon XP 3200+ vs the Pentium 4 3.0C/3.2C and higher processors.