Barcelona Architecture: AMD on the Counterattack
by Anand Lal Shimpi on March 1, 2007 12:05 AM EST- Posted in
- CPUs
New Prefetcher
Prefetching is done in many areas of the system and by many different components. When NVIDIA introduced its nForce2 chipset, it stressed the ability of its intelligent prefetcher to make use of a very wide, at the time, 128-bit memory bus. More recently, when Intel introduced its Core 2 processor family it stressed the importance of its three prefetchers per core in drastically reducing perceived memory latency.
AMD's K8 core had two prefetchers per core - one instruction and one data. The Barcelona core still retains the same number of prefetchers, but improves on them. The biggest change is that the data prefetcher now brings data directly into the L1 data cache, as opposed to the L2 cache in the K8. AMD looked at the accuracy of its core prefetchers and realized that they were doing quite well, so it only made sense to prefetch into a low latency L1 and avoid polluting the L2 cache. AMD has also increased the flexibility of its L1 instruction cache prefetcher to handle two outstanding requests to any address.
At first glance it looks like Intel's prefetchers in Core 2 are greater, at least in quantity, than what AMD has planned even for Barcelona. Remember that Intel's Core 2 processor features two data and one instruction prefetcher per core, plus an additional two L2 cache prefetchers, all of which are well managed as to not eat into "demand" bandwidth. At the same time, we must keep in mind that Intel needs these prefetchers to help mask its longer trip to main memory. From a CPU perspective, the advantage here is for Intel, but as a platform the true winner is tough to determine.
Each Barcelona core gets its own set of data and instruction prefetchers, but the major improvement is that there's a new prefetcher in town - a DRAM prefetcher. Residing within the memory controller where AMD previously never had any such logic, the new DRAM prefetcher takes a look at overall memory requests and attempts to pull data it thinks will be used in the future. As this prefetcher has to contend with the needs of four separate cores, it really helps the entire chip improve performance and can do a good job of spotting trends that would positively impact all cores. The DRAM prefetcher doesn't pull data into the CPU's L2 or L3 caches either; instead it features its own buffer to avoid polluting the caches. The buffer is approximately 20 - 30 cache lines in size and happens to be the same buffer that is used for Barcelona's write bursting we mentioned on the previous page.
Prefetching is done in many areas of the system and by many different components. When NVIDIA introduced its nForce2 chipset, it stressed the ability of its intelligent prefetcher to make use of a very wide, at the time, 128-bit memory bus. More recently, when Intel introduced its Core 2 processor family it stressed the importance of its three prefetchers per core in drastically reducing perceived memory latency.
AMD's K8 core had two prefetchers per core - one instruction and one data. The Barcelona core still retains the same number of prefetchers, but improves on them. The biggest change is that the data prefetcher now brings data directly into the L1 data cache, as opposed to the L2 cache in the K8. AMD looked at the accuracy of its core prefetchers and realized that they were doing quite well, so it only made sense to prefetch into a low latency L1 and avoid polluting the L2 cache. AMD has also increased the flexibility of its L1 instruction cache prefetcher to handle two outstanding requests to any address.
At first glance it looks like Intel's prefetchers in Core 2 are greater, at least in quantity, than what AMD has planned even for Barcelona. Remember that Intel's Core 2 processor features two data and one instruction prefetcher per core, plus an additional two L2 cache prefetchers, all of which are well managed as to not eat into "demand" bandwidth. At the same time, we must keep in mind that Intel needs these prefetchers to help mask its longer trip to main memory. From a CPU perspective, the advantage here is for Intel, but as a platform the true winner is tough to determine.
Each Barcelona core gets its own set of data and instruction prefetchers, but the major improvement is that there's a new prefetcher in town - a DRAM prefetcher. Residing within the memory controller where AMD previously never had any such logic, the new DRAM prefetcher takes a look at overall memory requests and attempts to pull data it thinks will be used in the future. As this prefetcher has to contend with the needs of four separate cores, it really helps the entire chip improve performance and can do a good job of spotting trends that would positively impact all cores. The DRAM prefetcher doesn't pull data into the CPU's L2 or L3 caches either; instead it features its own buffer to avoid polluting the caches. The buffer is approximately 20 - 30 cache lines in size and happens to be the same buffer that is used for Barcelona's write bursting we mentioned on the previous page.
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Amiteriver - Tuesday, March 27, 2007 - link
Sounds groooovyNow lets just hope they have something good to plug it into.
trisweb2 - Friday, March 16, 2007 - link
I just want to say how refreshing it is to read an article written by Anand. He is a master of the English language; he perfectly communicates and explains every technical detail and I come away with a better understanding of whatever he's talking about.Thank you, Anand, for being a good writer!
MrWizard6600 - Thursday, March 22, 2007 - link
I Agree, Outstanding.No other site I know of gives nearly as many in depth details, and while ill admit my knowlage of some of the terms is sketchy, I got through that one with a good understanding.
Sounds like AMD has something to fight Core 2 against.
I do have one criticism:
I would have loved to have heard what Intels equivilent to all of AMDs technologies would be, mind you this criticism corrects it self toward the end of the artical.
stance - Monday, March 5, 2007 - link
Remember AMD's old president and CEO Jerry Sanders with commentslike "We will see what we see" and "More bang for your buck" I
cannot wait to see duel socket motherboards with two four core
Barcelona's working their magic. reminds me of Carol shelby
when he brought the Cobra out for road test. exciting is not
the word, jaw droping performance? Don't take Richard's Statements
lightly
lordsnow - Sunday, March 4, 2007 - link
Does anyone have any idea how compatible the "Barcelona" CPU will be with current motherboards? When it comes out, does it need a new n-phase voltage regulator, for example?the reason I'm asking is, I want to upgrade and with the current state of affairs was going to go for a C2D CPU. But with these Barcelona CPU's due out I may stick with AMD - get a AM2 motherboard and cheap AM2 CPU and upgrade to the Barcelona CPU at a later date. But I have to be sure that whatever motherboard I buy now will be 100% Barcelona compatible.
Can anyone inform us about what the situation is in this regard?
coldpower27 - Sunday, March 4, 2007 - link
Barcelona being the server variant will be compatible with the Socket F infrastructure, while Agena will be a Socket AM2+ processor compatible with exisiting Socket AM2 infrastructure.lordsnow - Sunday, March 4, 2007 - link
Any ideas as to what kind of features a user will be missing by dropping a AM2+ "Agena" CPU into a AM2 socket? The enhanced Power Saving features, perhaps?chucky2 - Sunday, March 4, 2007 - link
I asked above and non-AnandTech folks like you and I said it would...but no one from AnandTech themselves jumped right in to give an affirmative.I asked for links from AMD's own website confirming that Agena and Kuma would work in current AM2 motherboards, and no one posted back.
Right now the AM2+ CPU's will work in current AM2 boards rumor is just that, a rumor...when AMD themselves confirm it, or a site such as AnandTech confirms it with AMD and reports on it, then I'll believe it.
Until then, it's <i>probable</i> that AM2+ will work in current AM2 motherboards...if you're willing to take the risk I say go for it, else, wait until we have an official answer one way or the other.
JMHO...
Chuck
Calin - Saturday, March 3, 2007 - link
"Intel regained the undisputed performance crown it hadn't seen ever since the debut of AMD's Athlon 64."Intel in fact lost the "undisputed performance king" title during the early lifetime of the K7 architecture. The Pentium !!! was faster at some tasks and slower at others (games) than the K7. Before that, the Pentium II was better than the K6-2 (the K6-3 had better IPC than Pentium3, but was slower in MHz)
coldpower27 - Sunday, March 4, 2007 - link
Intel had the undisputed performance crown again with the Athlon XP 3200+ vs the Pentium 4 3.0C/3.2C and higher processors.