To compare a potential 16Gb/s (per pin) GDDR5x or GDDR6 to HBM2:
HBM2 2-die bandwidth: 512GB/s (Vega seems to be using a cut-down bus for some reason, with the published 480GB/s speeds) To match this with 16GB/s GDDR5X you would need a 256bit bus. Many GPUs already exceed this, so matching two-stack HBM2 bandwidth with discrete GDDR is not a difficult task.
For 4-stack HBM2, you'd need a 512GB GDDR bus. IIRC the last GPU to have a bus that wide was the GTX285 with a GDDR3 bus. A 384bit wide bus is not out of the question and is used in current chips, so that gives 696GB/s vs. 4-stach HBM2's 1024GB/s.
The point for consumer GPUs is rather moot though, raw memory throughput does not seem to be a limiting factor in any current engine.
The mining crowd would disagree on memory throughput not being a limiting factor. For gaming I agree, at least until a game engine actually uses 4k res textures.
Well, the mining crowd could avoid that memory bottleneck completely (btw it's more about latency than bandwidth for Ethereum) if they wouldn't insist on creating other algorithms (than what Bitcoin uses), just so they can not be efficiently run on ASICs. They're deliberately burning energy, so to say.
It doesn't matter what the preferred miner for a specific coin is, the end result is always that the red queens race is run with ever more participants until:
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babadivad - Sunday, June 18, 2017 - link
Is it still limited to 1 GB per chip?ImSpartacus - Sunday, June 18, 2017 - link
No, the GDDR5X spec allows for up to 16Gb and the GDDR6 spec allows for up to 32Gb.The table at the source suggests Micron plans for 8Gb GDDR5X and 8 & 16Gb GDDDR6.
DanNeely - Sunday, June 18, 2017 - link
"The company is reporting that they've been able to hit Gbps data rates in the lab on their latest generation of GDDR5X devices, "You're missing a number here.
ImSpartacus - Sunday, June 18, 2017 - link
It's 16 Gbps.menting - Sunday, June 18, 2017 - link
"At present, HBM offers the greatest potential bandwidth"...Doesn't HMC offer the greatest potential bandwidth (and not HBM)?
DanNeely - Sunday, June 18, 2017 - link
Is HMC actually in use anywhere, or is it still a lab tech hoping to break into production somewhere?Adramtech - Sunday, June 18, 2017 - link
Dan, HMC is being applied herehttps://www.hpcwire.com/2017/06/14/ska-astronomy-p...
edzieba - Monday, June 19, 2017 - link
HMC is used in some Xeon Phi SKUs: https://www.micron.com/products/hybrid-memory-cube...menting - Monday, June 19, 2017 - link
I know at least 3. One is the one that Adramtech linked.The others are:
Fujitsu supercomputer: https://www.fujitsu.com/global/Images/primehpc-fx1...
The last one is Juniper: Juniper QFX10000 series.
FreckledTrout - Monday, June 19, 2017 - link
Outside of very limited cases HMC hasn't really taken off, costs maybe for on die memory? Im not sure but micron is also the once developing HMC.edzieba - Monday, June 19, 2017 - link
To compare a potential 16Gb/s (per pin) GDDR5x or GDDR6 to HBM2:HBM2 2-die bandwidth: 512GB/s (Vega seems to be using a cut-down bus for some reason, with the published 480GB/s speeds)
To match this with 16GB/s GDDR5X you would need a 256bit bus. Many GPUs already exceed this, so matching two-stack HBM2 bandwidth with discrete GDDR is not a difficult task.
For 4-stack HBM2, you'd need a 512GB GDDR bus. IIRC the last GPU to have a bus that wide was the GTX285 with a GDDR3 bus. A 384bit wide bus is not out of the question and is used in current chips, so that gives 696GB/s vs. 4-stach HBM2's 1024GB/s.
The point for consumer GPUs is rather moot though, raw memory throughput does not seem to be a limiting factor in any current engine.
Santoval - Monday, June 19, 2017 - link
"For 4-stack HBM2, you'd need a 512GB GDDR bus"Presumably you meant "512 bit bus".
patrickjp93 - Monday, June 19, 2017 - link
R9 390X, but thanks for playing.ImSpartacus - Monday, June 19, 2017 - link
Vega isn't using a cut down bus.2 Gbps HBM2 is not available. The per pin speed is lower, not the bus.
StevoLincolnite - Monday, June 19, 2017 - link
I miss the days when they used Mhz as the denominator for DRAM.FreckledTrout - Monday, June 19, 2017 - link
The mining crowd would disagree on memory throughput not being a limiting factor. For gaming I agree, at least until a game engine actually uses 4k res textures.MrSpadge - Monday, June 19, 2017 - link
Well, the mining crowd could avoid that memory bottleneck completely (btw it's more about latency than bandwidth for Ethereum) if they wouldn't insist on creating other algorithms (than what Bitcoin uses), just so they can not be efficiently run on ASICs. They're deliberately burning energy, so to say.baka_toroi - Tuesday, June 20, 2017 - link
Do you fail to see why an ASIC focused cryptocurrency is a bad thing?DanNeely - Tuesday, June 20, 2017 - link
It doesn't matter what the preferred miner for a specific coin is, the end result is always that the red queens race is run with ever more participants until:amortized_cost_of_miners + power_cost = value_of_coins_mined.
Zizy - Monday, June 19, 2017 - link
390X was the last with 512b bus. It was not that long ago, and not that impossible to happen again.