Just because you can't think of any real-world use cases, does not mean they don't exist. For me it would be very important to increase bandwidth between my Quadro cards (currently I have to use NVlink between pairs of cards).
No PCIe 5.0 is not dead. PCIe 4.0 will live on in desktops and slowly make its way into laptops at some point. It's just PCIe 5.0 and now PCIe 6.0 have so much bandwidth their use cases are server related. You will not see Intel or AMD with greater than PCIe 4.0 in non-server CPU's in a very long time, think 5 years out and that may still be early.
I really, really wish for a quick implementation of PCIe 5.0 in consumers chip as it might help bring protocols that relates to Non Volatile Memory (NVM) like CXL, Gen-z,...
A successor to the 7nm Qualcomm Snapdragon 8cx, done in 5nm with 5G and support for Non-Volatile-Memory (NVM) would enable many innovations to happen...
It might well be true that I will be 5 years until we see something better than 4.0, but my point is we are just starting to transition to 4.0 right now, so it will be a while until any major players decide to start planning for the next thing. When they do, 6.0 draft will be finalized, and it just won't make any sense to choose 5.0 spec when 6.0 spec is ready.
Intel might be planning to skip 4.0 and go to 5.0, and if they do, it's will be a bad move, because AMD is most likely going to 6.0 after 4.0, so they will again be ahead when they release it.
It's probably prudent to point out that it would be a bad idea for a company that is making a chipset like AMD or Intel to skip PCIe 5.0. Just like PCIe 4.0 over 3.0, the number of wires in the motherboard increases dramatically as does the chipset's power consumption. If you skip a generation you are setting yourself up for more issues as you now have to find space for drastically more interconnects and somehow have to make your chipset 4 times as power efficient.
Given that AMD had to increase the number of layers on X570 motherboards and the power consumption is high (15w), I don't see PCIe 6.0 being a good solution anytime soon. First we need to see PCIe 4.0 with lower power consumption and without the requirement of adding more PCB layers (which is expensive). Then we can start talking about PCIe 5.0 and eventually PCIe 6.0.
The new 6.0 standard is changing to "pulse amplitude modulation with 4 levels (PAM-4) encoding" rather than NRZ - "non-return to zero." Since they are touting backwards compatibility, it seems like new PCIe 6.0 components will need to be able to both encode transfers in NRZ when part of a < 6.0 chain, and encode in the new PAM4 format only used with components that are 6.0 ready.
I'm guessing it will take a bit more work to go to 6.0 than it will to go to 5.0. Who knows, perhaps putting any < 6.0 component into a 6.0 slot will stop your 6.0 components from reaching their maximum speed.
With all that, why not just skip 5.0 & go straight to 6.0? (shrug)
PCIe uses point to point links to form a packet switched network. The speed and width of one link has no effect on the speed or width that gets negotiated for another link elsewhere in the system. You will be able to have a PCIe 6 link operating between a peripheral device and a PCIe switch even if the link between that switch and the CPU is operating at gen5 or earlier speeds. You will be able to use PCIe 6 speeds in one expansion slot even if the device in the next slot is running at a lower speed. This is how PCIe compatibility has always worked.
The only things that will force a slower connection between two endpoints that both support a particular generation of PCIe are: inadequate analog signal quality (usually due to connector insertion loss), or older-generation redrivers or retimers (only found in servers so far).
PCIe is not a shared bus, rather point to point. Only reason say a PCIe 3.0 device would down grade the performance of a PCIe 6.0 device is if something like the base clock is shared beyond how a controller bifurcates. Devices today handle mixing 4.0, 3.0, 2.0 and 1.0 devices rather well.
Oh no, I was just reminiscing farther back, like in the early days of PCI (and even back in the days of ISA/EISA), not PCIe. You had some PCI components that would run at 33Mhz and some more advanced ones at 66Mhz, so you didn't want to accidentally slow down your 66MHz.
Which is resolved in one of two ways: - either Intel gets their act together AND/OR - the competitors for whom PCIe6 matters (server/data warehouse, so AMD, Graviton, Nuvia, Ampere, ...) will provide PCIe 6 instead.
2021 is the target year of the final release of the PCIe 6.0 spec, not of any products. No PCIe 6.0 products will be available next year, except perhaps some testing / developing / prototyping kits. The final spec of PCIe 5.0 was released on May 2019, and we've still seen no PCIe 5.0 products - with the exception, I think, of a couple of Intel FPGAs which are for a very specialized market.
So, at best, 2020 will be the year PCIe 4.0 becomes widely available. Then in 2021 we might get the first PCIe 5.0 products, with wide availability in 2022. Hence the earliest possible release of PCIe 6.0 should be in 2023 (limited), with wide availability in 2024. This assumes that new PCIe versions will be released every 2 years on average. If they're instead released every 3 years both PCIe 5.0 and PCIe 6.0 will be pulled back even further.
p.s. PCIe 6.0 products will almost certainly get delayed more than PCIe 5.0 products due to a radically changed design. PCIe 1.0 to 5.0 uses NRZ signaling and no error correction. So at a low level they are the same protocol, just each new version is clocked higher.
PCIe 6.0 switches to PAM4 (only for PCIe 6.0 mode) and also employs Forward Error Correction (FEC), because PAM4 signaling is less robust and thus more prone to cross talk and interference. Since PCIe 6.0 retains backward compatibility with all previous PCIe versions, this means that NRZ support is also required.
So all PCIe 6.0 devices and controllers are required to support two signaling modes, PAM4 for PCIe 6.0 and NRZ for everything else. It goes without saying that this is going to complicate the implementation, deployment and probably the cost of PCIe 6.0 devices quite a bit. It doesn't help that PAM4 signaling is weaker, particularly at the high clocks the PCIe 6.0 mode requires. The reason they moved to PAM4 was to put a brake on the clock increases. PAM4 has twice the bits of NRZ (it's like moving from SLC to MLC flash), so for PCIe 6.0 they didn't need to increase clocks over PCIe 5.0
From spefication to full product... can take a year or more. But I would not be surpriced that if my next upgrade from 5 years from now could have pci 6.0 :)
It takes a long time to develop standards. Somewhere people are working on 6G wireless, but they aren't talking loudly about it because people are sick and tired of hearing about 5G even though it isn't here yet.
Intel also takes a lot of blame for PCI4's slow rollout. All of the other high-performance chip vendors have moved on past PCI3, even Intel is rolling out PCI4 peripherals, but Intel-x86 support for PCI4 is still dead in the water.
I believe Intel decided to wait to PCI 5.0 for support. I would not blame it on Intel. The big question why is PCI coming out with these specifications so quickly - they are not the one that are actually doing the implementation.
Has anybody actually determine what kind of hardware is required to pump out 64 GT/s.
ahh there it is, the positive hstewart intel spin, on something negitive against intel. i dont think he has EVER said anything bad about his beloved intel. even when others refute his positivity with proof.
I think Intel will upgrade someday, but when they say 2021 that might really be more like 2023, 2024 or something if 10 nm is involved.
For a long time I think Intel has starved their platform for I/O bandwidth. The press which is financed by Intel's advertising plus many victim users who've learned to blame themselves will deny that Intel's platform is bandwidth-starved, but it comes back to Intel's plan when Dempsey scaling ran out to eliminate other vendors from the BoM of laptops and desktop computers. In particular, the last thing they want you to do is get a good graphics card, or several of them. Don't you know that Intel Integrated Graphics are all you need?
On paper if you could really use all those PCIe lanes it wouldn't be so bad, but in real life you might find you have an i5 instead of an i7 or you might have a budget motherboard and practically you can't use all those lanes and you won't discover that until you try a year down the road. Building PCs nowadays seems worse than when you had to deal with IRQ conflicts on the ISA bus.
For a long time, Intel was trying to kill ATI and NVIDIA. NVIDIA was saved by deep learning and ethereum, whereas ATI merged with AMD and has been kept alive by APU sales for game consoles that keep alive the skills to make PC games for their chips.
Now Intel finally has parts that are too fast for PCI3 and they are changing their tune -- maybe even Xe will need something faster than a 2400 serial port when it finally comes out. But until now, Intel has wanted to crush anybody who makes hardware (except they've never tried to kill Synaptics, which I don't understand...)
I think the reason Intel's server CPUs haven't had more PCIe lanes is that they support up to 8-socket configurations and saw deman for PCIe lanes as a way to move more CPUs. Big OEMs bought into this, too. Just try configuring a Dell server for a GPU - you'll quickly find that you can only do it in a dual-CPU configuration.
I mean AT LEAST a dual-CPU configuration, if you use their mainstream 2-socket servers. In the single-CPU config, none of the x16 slots will be connected to socket 0.
The chart shows the wrong GB/s for bandwidth. Each version of PCIe is off by 1 generation. PCIe 1.0 is 4GB/s (x16) not 8GB (x16), 2.0 8GB/s (x16) not 16GB (x16), etc...
Where does copper connect end ? I thought that 32G/s/pair was already over practical limit for copper pair and any practical reach. And even that was done on FPGAs of astronomical price and with few transceivers.
So PCIe switched to QAM and is going for even finer mopdulations.
ISn't this practically raping the initial PCIe concepts ? Hasn't the time long came for somebody to come with photonic Rx/Tx macro for new geometries ?
PCI SIG really screwed the pooch after the ratification of the 3.0 standard
We've had products featuring PCI-e 3.0 since 2011. It's 2020 and you can only get 4.0 on a few AMD motherboard (zero Intel) and not only is 5.0 here, but 6.0 next year? Please.
The specification has to be established and published before hardware oems can even hope to design controllers and then final AICs to make use of the interface. It's normal for the spec to be published a few years before you see products. The pci spec isn't intended for consumers, it's to guide hardware designers and engineers.
I'm well aware of the certification process for revisions to the PCI-e protocol. My argument is that the certification body dropped the ball after PCI-e 3.0 and we're now paying the price.
Nope. Newset gfenerations are aimed at most advanced, cutingh edge silicon. So afte rthe standard comes out, you see only a few cutting edge components for supercomputers. Then, after some time you get to see components for datacenters etc.
Then, after some time you get to see first, most advanced server boards and THEN they start to trickle into most expensive consumer products.
So, if you plan to wait for PCIe v6, you'll wait for quite some time.
Ordinary tech has problems even with PCIe4 ( like cooler on AMD's chipset etc), what would you do with 4x faster ( ond presumably at least 4x more power hungry) PCIe6 ?
Would you be fine with your chipset churning EXTRA 60W with nothing to show for it ?
Generally, for PCIe, it gets deployed top to bottom when it's available. It's the proprietary stuff (NVLINK) the starts at the top and /sometimes/ trickles down. More often than not, the proprietary stuff dies off as it gets replaced by standardized alternatives.
This sort of tech is where trends fail to extrapolate. PCIe 5.0 and 6.0 are so power-hungry and expensive to implement, and these aren't problems that can necessarily be solved by normal technological advances like smaller process nodes.
How can you even expect PCI 6.0 hardware before the spec is released? Spec will be released in 2021. It will probably take 2-3 yrs after that to see PCI 6.0 products in consumer space. We don't even have PCI 5.0 products yet.
A lot of people are saying that there is no need for more than PCI 4.0 on the desktop - They are forgetting that for AMD PCI is the interconnect between chiplets - I/O die and the I/O die and the Southbridge chip. If AMD needs additional bandwidth on these connections it can change the PCI version and the desktop may just gain faster PCI slots.
Not true. There are different rules for internal, on the chip interconnect and PCIe lanes which have to mantain signal integrity relativelly far off-the chip and possibly even on cable.
IF link between chiplets can be less than an inch long, on much higher quality substrate, smaller geometries ( ie silver or even gold traces between chiplets) and tightly equalized path lengts.
Also, microvia is "cheaper" than a full I/O pad, so the busses can be wider AND faster...
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fred666 - Friday, February 21, 2020 - link
Given the slow adoption of PICe 4.0, I doubt we will really be at PCIe 6.0 by 2021. Except maybe some niche products.UltraWide - Friday, February 21, 2020 - link
They can skip versions to the latest, there is no rule that requires sequential implementation. :)mode_13h - Friday, February 21, 2020 - link
Since 6.0 builds on 5.0, I think it's more realistic to expect most vendors not to skip.p1esk - Friday, February 21, 2020 - link
5.0 is dead. I'm not going to buy 5.0 when I know 6.0 is around the corner.Sivar - Friday, February 21, 2020 - link
You should wait for PCIe 7.0. What possible real-world use could links with a mere 128GB/s or 256GB/s have?p1esk - Friday, February 21, 2020 - link
Just because you can't think of any real-world use cases, does not mean they don't exist. For me it would be very important to increase bandwidth between my Quadro cards (currently I have to use NVlink between pairs of cards).FreckledTrout - Friday, February 21, 2020 - link
LOL yeah but even PCIe 4.0 would do the trick for you let alone PCIe 7 :)rpg1966 - Saturday, February 22, 2020 - link
And if you need moar, then surely double or quadruple whatever you have now, is better than waiting forever for 8x whatever you have now.MDD1963 - Tuesday, February 25, 2020 - link
If I need more bandwidth than that offered by PCI-e 4.0, I will simply download more! :)mode_13h - Saturday, February 22, 2020 - link
It doesn't matter if you can think of a use case, if the technology is too expensive or impractical to implement for your market segment.FreckledTrout - Friday, February 21, 2020 - link
No PCIe 5.0 is not dead. PCIe 4.0 will live on in desktops and slowly make its way into laptops at some point. It's just PCIe 5.0 and now PCIe 6.0 have so much bandwidth their use cases are server related. You will not see Intel or AMD with greater than PCIe 4.0 in non-server CPU's in a very long time, think 5 years out and that may still be early.Diogene7 - Friday, February 21, 2020 - link
I really, really wish for a quick implementation of PCIe 5.0 in consumers chip as it might help bring protocols that relates to Non Volatile Memory (NVM) like CXL, Gen-z,...A successor to the 7nm Qualcomm Snapdragon 8cx, done in 5nm with 5G and support for Non-Volatile-Memory (NVM) would enable many innovations to happen...
antonkochubey - Friday, February 21, 2020 - link
AM2 was PCIe 2.0AM3 was PCIe 3.0
AM4 is [up to] PCIe 4.0
and AM5 is coming in a year or two ;)
p1esk - Friday, February 21, 2020 - link
It might well be true that I will be 5 years until we see something better than 4.0, but my point is we are just starting to transition to 4.0 right now, so it will be a while until any major players decide to start planning for the next thing. When they do, 6.0 draft will be finalized, and it just won't make any sense to choose 5.0 spec when 6.0 spec is ready.Intel might be planning to skip 4.0 and go to 5.0, and if they do, it's will be a bad move, because AMD is most likely going to 6.0 after 4.0, so they will again be ahead when they release it.
mode_13h - Friday, February 21, 2020 - link
LOL. Unless you're buying server hardware, you won't have any option other than 4.0.evernessince - Monday, February 24, 2020 - link
It's probably prudent to point out that it would be a bad idea for a company that is making a chipset like AMD or Intel to skip PCIe 5.0. Just like PCIe 4.0 over 3.0, the number of wires in the motherboard increases dramatically as does the chipset's power consumption. If you skip a generation you are setting yourself up for more issues as you now have to find space for drastically more interconnects and somehow have to make your chipset 4 times as power efficient.Given that AMD had to increase the number of layers on X570 motherboards and the power consumption is high (15w), I don't see PCIe 6.0 being a good solution anytime soon. First we need to see PCIe 4.0 with lower power consumption and without the requirement of adding more PCB layers (which is expensive). Then we can start talking about PCIe 5.0 and eventually PCIe 6.0.
mode_13h - Monday, February 24, 2020 - link
From what I've read, going from PCIe 4.0 to 5.0 is even more expensive (in terms of PCB costs) than going from 3.0 to 4.0.romrunning - Friday, February 21, 2020 - link
The new 6.0 standard is changing to "pulse amplitude modulation with 4 levels (PAM-4) encoding" rather than NRZ - "non-return to zero." Since they are touting backwards compatibility, it seems like new PCIe 6.0 components will need to be able to both encode transfers in NRZ when part of a < 6.0 chain, and encode in the new PAM4 format only used with components that are 6.0 ready.I'm guessing it will take a bit more work to go to 6.0 than it will to go to 5.0. Who knows, perhaps putting any < 6.0 component into a 6.0 slot will stop your 6.0 components from reaching their maximum speed.
With all that, why not just skip 5.0 & go straight to 6.0? (shrug)
Billy Tallis - Friday, February 21, 2020 - link
PCIe uses point to point links to form a packet switched network. The speed and width of one link has no effect on the speed or width that gets negotiated for another link elsewhere in the system. You will be able to have a PCIe 6 link operating between a peripheral device and a PCIe switch even if the link between that switch and the CPU is operating at gen5 or earlier speeds. You will be able to use PCIe 6 speeds in one expansion slot even if the device in the next slot is running at a lower speed. This is how PCIe compatibility has always worked.The only things that will force a slower connection between two endpoints that both support a particular generation of PCIe are: inadequate analog signal quality (usually due to connector insertion loss), or older-generation redrivers or retimers (only found in servers so far).
romrunning - Friday, February 21, 2020 - link
Ah, that's good. I'm glad we're not back to the days of one component forcing the whole bus to a slower speed.mode_13h - Friday, February 21, 2020 - link
Yeah, PCIe is not a bus.Kevin G - Friday, February 21, 2020 - link
PCIe is not a shared bus, rather point to point. Only reason say a PCIe 3.0 device would down grade the performance of a PCIe 6.0 device is if something like the base clock is shared beyond how a controller bifurcates. Devices today handle mixing 4.0, 3.0, 2.0 and 1.0 devices rather well.romrunning - Tuesday, February 25, 2020 - link
Oh no, I was just reminiscing farther back, like in the early days of PCI (and even back in the days of ISA/EISA), not PCIe. You had some PCI components that would run at 33Mhz and some more advanced ones at 66Mhz, so you didn't want to accidentally slow down your 66MHz.romrunning - Tuesday, February 25, 2020 - link
Of course, don't quote me on the above - lots of things change over the years, including my memory! :)III-V - Friday, February 21, 2020 - link
The standard will be finalized next year... products won't come until much later.A5 - Friday, February 21, 2020 - link
Yep. Realistically we'll start to see PCIe 5 products in 2021.fred666 - Friday, February 21, 2020 - link
or maybe even 2022FreckledTrout - Friday, February 21, 2020 - link
Sure yes, server products. Going to be a closer to 2030 when you see desktop products.mode_13h - Friday, February 21, 2020 - link
I'm not sure it will ever reach the desktop.nandnandnand - Friday, February 21, 2020 - link
Do they eventually need photonics on the motherboard to improve speeds?chophshiy - Friday, February 21, 2020 - link
Eventually. Notice how interfaces like USB 3.x/4 are getting shorter standard cables, heavier shielding, more expensive. Same principles.surt - Saturday, February 22, 2020 - link
Yes, and that's exactly why intel is massively investing in photonics and letting their other technologies lag.mode_13h - Saturday, February 22, 2020 - link
Perhaps, but they killed off Omnipath.name99 - Friday, February 21, 2020 - link
aka "given the slow adoption of PCIe by Intel"...Which is resolved in one of two ways:
- either Intel gets their act together AND/OR
- the competitors for whom PCIe6 matters (server/data warehouse, so AMD, Graviton, Nuvia, Ampere, ...) will provide PCIe 6 instead.
mode_13h - Friday, February 21, 2020 - link
Intel would already have PCIe 4.0-enabled server chips on the market, if their 10 nm didn't suck so hard.Santoval - Friday, February 21, 2020 - link
2021 is the target year of the final release of the PCIe 6.0 spec, not of any products. No PCIe 6.0 products will be available next year, except perhaps some testing / developing / prototyping kits. The final spec of PCIe 5.0 was released on May 2019, and we've still seen no PCIe 5.0 products - with the exception, I think, of a couple of Intel FPGAs which are for a very specialized market.So, at best, 2020 will be the year PCIe 4.0 becomes widely available. Then in 2021 we might get the first PCIe 5.0 products, with wide availability in 2022. Hence the earliest possible release of PCIe 6.0 should be in 2023 (limited), with wide availability in 2024. This assumes that new PCIe versions will be released every 2 years on average. If they're instead released every 3 years both PCIe 5.0 and PCIe 6.0 will be pulled back even further.
Santoval - Friday, February 21, 2020 - link
p.s. PCIe 6.0 products will almost certainly get delayed more than PCIe 5.0 products due to a radically changed design. PCIe 1.0 to 5.0 uses NRZ signaling and no error correction. So at a low level they are the same protocol, just each new version is clocked higher.PCIe 6.0 switches to PAM4 (only for PCIe 6.0 mode) and also employs Forward Error Correction (FEC), because PAM4 signaling is less robust and thus more prone to cross talk and interference. Since PCIe 6.0 retains backward compatibility with all previous PCIe versions, this means that NRZ support is also required.
So all PCIe 6.0 devices and controllers are required to support two signaling modes, PAM4 for PCIe 6.0 and NRZ for everything else. It goes without saying that this is going to complicate the implementation, deployment and probably the cost of PCIe 6.0 devices quite a bit. It doesn't help that PAM4 signaling is weaker, particularly at the high clocks the PCIe 6.0 mode requires.
The reason they moved to PAM4 was to put a brake on the clock increases. PAM4 has twice the bits of NRZ (it's like moving from SLC to MLC flash), so for PCIe 6.0 they didn't need to increase clocks over PCIe 5.0
descendency - Saturday, February 22, 2020 - link
It won't be available in a product. It will be ratified as a standard (v1.0)... but you likely won't see it in consumer products for years.haukionkannel - Friday, February 21, 2020 - link
From spefication to full product... can take a year or more. But I would not be surpriced that if my next upgrade from 5 years from now could have pci 6.0 :)mode_13h - Friday, February 21, 2020 - link
Only if you're buying a server board.colinstu - Friday, February 21, 2020 - link
Wait... whatever happened to PCIe 5.0?fred666 - Friday, February 21, 2020 - link
was approved in 2019, and yet we have no sign of products supporting it anytime soon.PaulHoule - Friday, February 21, 2020 - link
It takes a long time to develop standards. Somewhere people are working on 6G wireless, but they aren't talking loudly about it because people are sick and tired of hearing about 5G even though it isn't here yet.Intel also takes a lot of blame for PCI4's slow rollout. All of the other high-performance chip vendors have moved on past PCI3, even Intel is rolling out PCI4 peripherals, but Intel-x86 support for PCI4 is still dead in the water.
HStewart - Friday, February 21, 2020 - link
I believe Intel decided to wait to PCI 5.0 for support. I would not blame it on Intel. The big question why is PCI coming out with these specifications so quickly - they are not the one that are actually doing the implementation.Has anybody actually determine what kind of hardware is required to pump out 64 GT/s.
sa666666 - Friday, February 21, 2020 - link
Of course you wouldn't blame it on Intel. Have you ever blamed Intel for anything, especially when they truly deserved it? Of course not.Qasar - Saturday, February 22, 2020 - link
ahh there it is, the positive hstewart intel spin, on something negitive against intel.i dont think he has EVER said anything bad about his beloved intel. even when others refute his positivity with proof.
Toadster - Friday, February 21, 2020 - link
Ice Lake Server 2020 https://en.wikichip.org/wiki/intel/microarchitectu...mode_13h - Friday, February 21, 2020 - link
Sapphire Rapids is slated to feature it, in 2021:https://www.tomshardware.com/news/intel-server-ddr...
Given that Intel's CXL shares common foundations with PCIe 5.0, it's a safe bet that Intel will follow-through on this.
PaulHoule - Friday, February 21, 2020 - link
I think Intel will upgrade someday, but when they say 2021 that might really be more like 2023, 2024 or something if 10 nm is involved.For a long time I think Intel has starved their platform for I/O bandwidth. The press which is financed by Intel's advertising plus many victim users who've learned to blame themselves will deny that Intel's platform is bandwidth-starved, but it comes back to Intel's plan when Dempsey scaling ran out to eliminate other vendors from the BoM of laptops and desktop computers. In particular, the last thing they want you to do is get a good graphics card, or several of them. Don't you know that Intel Integrated Graphics are all you need?
On paper if you could really use all those PCIe lanes it wouldn't be so bad, but in real life you might find you have an i5 instead of an i7 or you might have a budget motherboard and practically you can't use all those lanes and you won't discover that until you try a year down the road. Building PCs nowadays seems worse than when you had to deal with IRQ conflicts on the ISA bus.
For a long time, Intel was trying to kill ATI and NVIDIA. NVIDIA was saved by deep learning and ethereum, whereas ATI merged with AMD and has been kept alive by APU sales for game consoles that keep alive the skills to make PC games for their chips.
Now Intel finally has parts that are too fast for PCI3 and they are changing their tune -- maybe even Xe will need something faster than a 2400 serial port when it finally comes out. But until now, Intel has wanted to crush anybody who makes hardware (except they've never tried to kill Synaptics, which I don't understand...)
mode_13h - Friday, February 21, 2020 - link
Uh, whatever.I think the reason Intel's server CPUs haven't had more PCIe lanes is that they support up to 8-socket configurations and saw deman for PCIe lanes as a way to move more CPUs. Big OEMs bought into this, too. Just try configuring a Dell server for a GPU - you'll quickly find that you can only do it in a dual-CPU configuration.
mode_13h - Friday, February 21, 2020 - link
I mean AT LEAST a dual-CPU configuration, if you use their mainstream 2-socket servers. In the single-CPU config, none of the x16 slots will be connected to socket 0.schujj07 - Friday, February 21, 2020 - link
The chart shows the wrong GB/s for bandwidth. Each version of PCIe is off by 1 generation. PCIe 1.0 is 4GB/s (x16) not 8GB (x16), 2.0 8GB/s (x16) not 16GB (x16), etc...sheh - Friday, February 21, 2020 - link
I guess they mean the full-duplex rate.mode_13h - Friday, February 21, 2020 - link
True, but the chart should make it clear. For things like graphics, data flows are not symmetric.shabby - Friday, February 21, 2020 - link
Is it safe to say that long delay between pcie 3 and 4 was because of intel not developing any new platforms and amd still sleeping?mode_13h - Friday, February 21, 2020 - link
I'd say lack of demand. Until NVMe SSDs and deployment of 100 Gigabit network really heated up, PCIe 3.0 was pretty adequate.mode_13h - Friday, February 21, 2020 - link
AI, as well.Qasar - Saturday, February 22, 2020 - link
well, intel did say mainstream doesnt need more then 4 cores......Brane2 - Friday, February 21, 2020 - link
Where does copper connect end ?I thought that 32G/s/pair was already over practical limit for copper pair and any practical reach.
And even that was done on FPGAs of astronomical price and with few transceivers.
So PCIe switched to QAM and is going for even finer mopdulations.
ISn't this practically raping the initial PCIe concepts ?
Hasn't the time long came for somebody to come with photonic Rx/Tx macro for new geometries ?
techguymaxc - Friday, February 21, 2020 - link
PCI SIG really screwed the pooch after the ratification of the 3.0 standardWe've had products featuring PCI-e 3.0 since 2011. It's 2020 and you can only get 4.0 on a few AMD motherboard (zero Intel) and not only is 5.0 here, but 6.0 next year? Please.
Ej24 - Friday, February 21, 2020 - link
The specification has to be established and published before hardware oems can even hope to design controllers and then final AICs to make use of the interface. It's normal for the spec to be published a few years before you see products. The pci spec isn't intended for consumers, it's to guide hardware designers and engineers.techguymaxc - Friday, February 21, 2020 - link
I'm well aware of the certification process for revisions to the PCI-e protocol. My argument is that the certification body dropped the ball after PCI-e 3.0 and we're now paying the price.mode_13h - Friday, February 21, 2020 - link
How are you paying the price?mode_13h - Friday, February 21, 2020 - link
A number of ARM servers also have PCIe 4.0, and POWER had it since like 2018.damianrobertjones - Friday, February 21, 2020 - link
Suggestion to everyone: Do not buy a new motherboard, or computer, with pcie4 until 2021.I bet we'd have pci e 6 by the end of THIS year.
It IS all about milking the max amount of cash over the longest period of time. Tech could be so very far ahead if it wasn't for $$$$
Brane2 - Friday, February 21, 2020 - link
Nope. Newset gfenerations are aimed at most advanced, cutingh edge silicon.So afte rthe standard comes out, you see only a few cutting edge components for supercomputers.
Then, after some time you get to see components for datacenters etc.
Then, after some time you get to see first, most advanced server boards and THEN they start to trickle into most expensive consumer products.
So, if you plan to wait for PCIe v6, you'll wait for quite some time.
Ordinary tech has problems even with PCIe4 ( like cooler on AMD's chipset etc), what would you do with 4x faster ( ond presumably at least 4x more power hungry) PCIe6 ?
Would you be fine with your chipset churning EXTRA 60W with nothing to show for it ?
chophshiy - Friday, February 21, 2020 - link
Generally, for PCIe, it gets deployed top to bottom when it's available. It's the proprietary stuff (NVLINK) the starts at the top and /sometimes/ trickles down. More often than not, the proprietary stuff dies off as it gets replaced by standardized alternatives.mode_13h - Friday, February 21, 2020 - link
This sort of tech is where trends fail to extrapolate. PCIe 5.0 and 6.0 are so power-hungry and expensive to implement, and these aren't problems that can necessarily be solved by normal technological advances like smaller process nodes.aadish151 - Friday, February 21, 2020 - link
How can you even expect PCI 6.0 hardware before the spec is released? Spec will be released in 2021. It will probably take 2-3 yrs after that to see PCI 6.0 products in consumer space. We don't even have PCI 5.0 products yet.mode_13h - Friday, February 21, 2020 - link
You'll die of old age, waiting for a desktop board with PCIe 6.0.RogerAndOut - Friday, February 21, 2020 - link
A lot of people are saying that there is no need for more than PCI 4.0 on the desktop - They are forgetting that for AMD PCI is the interconnect between chiplets - I/O die and the I/O die and the Southbridge chip. If AMD needs additional bandwidth on these connections it can change the PCI version and the desktop may just gain faster PCI slots.Brane2 - Friday, February 21, 2020 - link
Not true. There are different rules for internal, on the chip interconnect and PCIe lanes which have to mantain signal integrity relativelly far off-the chip and possibly even on cable.IF link between chiplets can be less than an inch long, on much higher quality substrate, smaller geometries ( ie silver or even gold traces between chiplets) and tightly equalized path lengts.
Also, microvia is "cheaper" than a full I/O pad, so the busses can be wider AND faster...
brunis.dk - Saturday, February 22, 2020 - link
So, Intel is still in 2010? ..back2future - Monday, December 20, 2021 - link
considering SSDs power requirements estimation for PCIe 5.0 (TDP <14W) and 6.0 (up to 28W) https://www.tweaktown.com/news/82402/phison-talks-...