The RISC-V ISA and execution rules are open and free to utilize but the underlying Micro-Architecture that Tenstorrent created to implement the RISC-V ISA is Tenstorrent's IP. So the Instruction Decoders on the cores that break down the RISC-V ISA instructions into Micro-Ops(Single Micro-ops or Multiple Micro-ops) and the micro-op execution engine is all Tensetorrent's IP. The Cache subsystems and Memory controllers are all Tensetorrents's design etc.
But there may be 3rd party SerDes IP from other providers as well as IP blocks that may be licensed from others if not created in-house. But really the SOC client may be the one licensing the 3rd party IP and Tensetorrent just providing a working Ascalon core/cores complex that can hardware interoperate with that client's hardware IP/3rd party licensed hardware IP.
And all ISA are just execution templates with execution rules to follow and Memory Coherency models to enforce etc! But the actual hardware is not the ISA but a custom implementation engineered to execute the ISA.
Even open software isn't the same. Linux is open source. Android isn't really open source: its development is not open, only releases are. Some functionality is contingent on device manufacturers entering licensing agreement with Google.
The fact that RISC V is open is still an advantage. In the same way that Linux running on ARM-based server hardware benefits from the work Google and others have invested in the ARM port of Linux.
The RISC-v creators used the open license... dang, even wikipedia just links to a news article that uses the catch-all phrase, "Open License". Fail.
Ah, they used CC4. CC4 has a copy-left clause. I wonder why it doesn't appear to apply here, since the processor is obviously a derivative work, being an actual physical implementation of a textual description.
I understand what you're saying. It seems their stance is that the hardware implementation is separate from the specification. Only the specification is open and free to use. A RISC-V implementation, on the other hand, can be either closed or open source. According to their FAQ, the confusion is coming from the difference between open source and open standard, and RISC-V falls under the latter.
"The closest analogy to the RISC-V specification is a book that defines words, like a dictionary. A dictionary can’t run programs.
"If our company builds a RISC-V implementation, is it required to release its source code for the RISC-V core? // No, the source code can be completely closed."
RISC-V offers 128-bit addressing. Who knows if anybody is using it yet - probably not. RISC-V is also free. Arm has hefty license fees and also per-chip royalties.
I'm afraid that for Tenstorrent it is AI first, and RISC-V second, and we're never going to see a general purpose CPU from them — only as control processor in some kind of AI accelerator.
RISC V is very successful in many places where e. g. interoperability is not as important. Harddrive controllers is an example that comes to mind (to my knowledge, Western Digital uses RISC V cores in its HD controllers). But it need not take over all niches.
Part of the licensing agreement with ARM are tests that your cores comply with the ARM ISA spec. For RISC V such an ultimate authority is missing. This has advantages and disadvantages. It is great if you don't actually need interoperability. But it is detrimental if several companies build their own cores and subtle differences lead to problems.
Funny to see how Chinese malevolence towards Taiwan has revitalized American and Japanese semiconductor manufacturing. Was that the goal, comrade Xi? Or was the goal to revitalize American and Japanese military industrial complex? Because you’re doing that too. Also, the EU now doesn’t trust you, nor do your neighbors. All to threaten a little island that you can only control if you destroy, leaving it useless to you.
I’d love to play a game of multiplayer Civ with this dope.
Well, the beautifully-moral, US-backed Israel is playing a brilliant game of Civilization in the sands of Palestine as we speak. At this rate, they'll be teaching even China a thing or two.
China has nukes. China can reduce costs and undercut prices by stealing western technology and IP. Xi cares what we think about as much as Putin. The whole world needs to finally agree to build an economic wall around these countries until they wake up and join the 21st century. ISR too. SA too. Heck the whole ME.
The "nm" or "um" rating of a technology was NEVER EVER the transistor pitch. It was ALWAYS the gate length, which is not the same thing. Jeebus read a Wikipedia article. 5/4/3/2 nm technologies typically have gate pitches around the 50nm range. Gate length is now meaningless because the gate construction is so wildly different than the old planar.
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ballsystemlord - Wednesday, February 28, 2024 - link
Umm, what exactly was licensed on the RISC-V processor? RISC-V is open HW.FWhitTrampoline - Wednesday, February 28, 2024 - link
The RISC-V ISA and execution rules are open and free to utilize but the underlying Micro-Architecture that Tenstorrent created to implement the RISC-V ISA is Tenstorrent's IP. So the Instruction Decoders on the cores that break down the RISC-V ISA instructions into Micro-Ops(Single Micro-ops or Multiple Micro-ops) and the micro-op execution engine is all Tensetorrent's IP. The Cache subsystems and Memory controllers are all Tensetorrents's design etc.But there may be 3rd party SerDes IP from other providers as well as IP blocks that may be licensed from others if not created in-house. But really the SOC client may be the one licensing the 3rd party IP and Tensetorrent just providing a working Ascalon core/cores complex that can hardware interoperate with that client's hardware IP/3rd party licensed hardware IP.
And all ISA are just execution templates with execution rules to follow and Memory Coherency models to enforce etc! But the actual hardware is not the ISA but a custom implementation engineered to execute the ISA.
Threska - Thursday, February 29, 2024 - link
Right, some forget open hardware isn't the same as open software.OreoCookie - Saturday, March 2, 2024 - link
Even open software isn't the same. Linux is open source. Android isn't really open source: its development is not open, only releases are. Some functionality is contingent on device manufacturers entering licensing agreement with Google.The fact that RISC V is open is still an advantage. In the same way that Linux running on ARM-based server hardware benefits from the work Google and others have invested in the ARM port of Linux.
ballsystemlord - Thursday, February 29, 2024 - link
The RISC-v creators used the open license... dang, even wikipedia just links to a news article that uses the catch-all phrase, "Open License". Fail.Ah, they used CC4. CC4 has a copy-left clause. I wonder why it doesn't appear to apply here, since the processor is obviously a derivative work, being an actual physical implementation of a textual description.
GeoffreyA - Friday, March 1, 2024 - link
I understand what you're saying. It seems their stance is that the hardware implementation is separate from the specification. Only the specification is open and free to use. A RISC-V implementation, on the other hand, can be either closed or open source. According to their FAQ, the confusion is coming from the difference between open source and open standard, and RISC-V falls under the latter."The closest analogy to the RISC-V specification is a book that defines words, like a dictionary. A dictionary can’t run programs.
"If our company builds a RISC-V implementation, is it required to release its source code for the RISC-V core? // No, the source code can be completely closed."
https://riscv.org/about/faq/
ballsystemlord - Friday, March 1, 2024 - link
Thanks, that makes things much clearer!Yojimbo - Thursday, February 29, 2024 - link
RISC-V is a swamp-in-waiting.vladpetric - Monday, March 4, 2024 - link
Microarchitecture - things like the front-end (branch prediction though not only), execution engine, back-end.Getting these right is a lot more complicated than the instruction set (decoding it, executing it, etc)
peevee - Tuesday, March 5, 2024 - link
RISC-V by itself brings nothing compared to ARMv8. Prove me wrong.GeoffreyA - Wednesday, March 6, 2024 - link
Technically, there's likely not much of a difference in the result, though I believe it's simpler. Being free and open is good.do_not_arrest - Wednesday, March 6, 2024 - link
RISC-V offers 128-bit addressing. Who knows if anybody is using it yet - probably not. RISC-V is also free. Arm has hefty license fees and also per-chip royalties.GeoffreyA - Thursday, February 29, 2024 - link
Ascalon sounds quite strong. It will be interesting to see how it performs.Dante Verizon - Thursday, February 29, 2024 - link
If it were next year I'd be impressed, but by 2027 the competition will be up to scratch...Findecanor - Thursday, February 29, 2024 - link
I'm afraid that for Tenstorrent it is AI first, and RISC-V second, and we're never going to see a general purpose CPU from them — only as control processor in some kind of AI accelerator.OreoCookie - Saturday, March 2, 2024 - link
Why is that necessarily a bad thing?RISC V is very successful in many places where e. g. interoperability is not as important. Harddrive controllers is an example that comes to mind (to my knowledge, Western Digital uses RISC V cores in its HD controllers). But it need not take over all niches.
Part of the licensing agreement with ARM are tests that your cores comply with the ARM ISA spec. For RISC V such an ultimate authority is missing. This has advantages and disadvantages. It is great if you don't actually need interoperability. But it is detrimental if several companies build their own cores and subtle differences lead to problems.
Blastdoor - Friday, March 1, 2024 - link
Funny to see how Chinese malevolence towards Taiwan has revitalized American and Japanese semiconductor manufacturing. Was that the goal, comrade Xi? Or was the goal to revitalize American and Japanese military industrial complex? Because you’re doing that too. Also, the EU now doesn’t trust you, nor do your neighbors. All to threaten a little island that you can only control if you destroy, leaving it useless to you.I’d love to play a game of multiplayer Civ with this dope.
GeoffreyA - Friday, March 1, 2024 - link
Well, the beautifully-moral, US-backed Israel is playing a brilliant game of Civilization in the sands of Palestine as we speak. At this rate, they'll be teaching even China a thing or two.do_not_arrest - Wednesday, March 6, 2024 - link
China has nukes. China can reduce costs and undercut prices by stealing western technology and IP. Xi cares what we think about as much as Putin. The whole world needs to finally agree to build an economic wall around these countries until they wake up and join the 21st century. ISR too. SA too. Heck the whole ME.peevee - Tuesday, March 5, 2024 - link
"2nm" is what really, 20nm transistor pitch? 30nm? 40nm? So tired of the fraud.do_not_arrest - Wednesday, March 6, 2024 - link
The "nm" or "um" rating of a technology was NEVER EVER the transistor pitch. It was ALWAYS the gate length, which is not the same thing. Jeebus read a Wikipedia article. 5/4/3/2 nm technologies typically have gate pitches around the 50nm range. Gate length is now meaningless because the gate construction is so wildly different than the old planar.Santoval - Monday, March 11, 2024 - link
Though it was not clarified I assume "for edge" means AI inferencing, not training right? So this will not compete with Nvidia's GPUs..