ServerWorks HEsl: DDR bandwidth without DDR SDRAM

Photoshop 6 Performance

One of the biggest questions we get is how to build a powerful machine for heavy-duty image editing and while the Photoshop 4 MP benchmark from earlier on in this review provided some indication to the performance differences between the platforms we wanted to take a look at a more thorough comparison.

We turned to a little known benchmark called PSBench combined with Photoshop 6.0 to perform a time trial test of 21 filters and modifications to a 50MB TIFF file measuring 4830 x 3624. While this is a tad on the extreme side, we wanted to see truly what differences existed between these platforms if any and based on that, conclude whether professional image editing programs such as Photoshop are more likely to respond to more memory bandwidth or faster processors.

The details of the benchmark are found below which is a table of the average of three time trials for each filter/modification performed on the image. If you'd like to try your hands at the PSBench test script yourself, you can find it here. Remember that there are three PSBench scripts, a 10MB, 20MB and a 50MB test; we used the latter.

Interestingly enough, the two VIA platforms and the i840 perform within 1% of one another. The 133A manages to be slightly faster than the other two, quite possibly because of latency advantages (remember that PC133 SDRAM still has a lower latency than DDR SDRAM which has a lower latency than RDRAM) as well as pure platform maturity. But when you look at the big picture, the 133A is still no more than 1% faster than the Pro 266 or the i840.

In spite of how the other three platforms performed, the HEsl managed to distinguish itself from the competition by around 8%. Since there's very little tangible information that we know about the inner workings of the HEsl chipset we can only attribute this performance advantage to what we do know.

We do know that Photoshop was quite appreciative of the 133A's PC133 SDRAM (CL2) which was used on the HEsl as well. The fact that the HEsl has an effective 128-bit (64-bit interleaved) memory interface using this low-latency PC133 SDRAM could explain part of the performance advantage but there is still a portion that is up for grabs. Again, this could be attributed to efficient management of the memory/FSB bandwidth that is available through the use of caches and other performance tweaks.

Remember that the HEsl North Bridge is a 644-pin chip making it larger than both the i850's MCH and the AMD 761 North Bridge. They have to be using that added die space for something…