I'm not qualified to decide what metric to use and I really don't care as long as the main ingredient isn't an arbitrary figure which came into existence in a marketing department meeting.
Half the people that discuss this do not know what they are talking about. I read a lot of people saying that 'only Intel' has a true 'XXnm node'. However, the only company to ever make that claim was Intel itself and it was not backed up by third parties. Furthermore, evidence suggests that Intel may have fabricated that statement. I'm willing to bet that Samsung process is far superior to Intel's at this current point in time.
Samsung 10nm is less dense than TSMC 10nm due to being earlier, and this should make it as good or better than TSMC 10nm. And yes, both are significantly better than Intel's current 14nm process. TSMC and Samsung 7nm are also better than Intel 10nm.
"TSMC and Samsung 7nm are also better than Intel 10nm" Strange claim, there is a good consensus between analists that Intel 10nm is pretty on line with TSMC 7nm.....Samsung 7nm process is pretty unknown right now. Have you some informations that professional analists don't have??
"TSMC and Samsung 7nm are also better than Intel 10nm"
Personally I think this naming of 10nm vs 7nm process today reminds me the frequency wars in the past but in opposite direction. I believe the real thing is how many transistors can be pack in same area. From specs what I hear about what is coming in Cannon Lake and such and other slide I seen on Intel's process - I think we probably find that Intel's process is totally going to surprise people especially Samsung and TSMC.
But truthfully, it any ones guess until Intel releases - the news today about Icy Lake look very promising - especially in technical specs. I really love the faster REP MOV - if done right ( backward application compatible ) this could be a serious game change - I done almost 7 years straight of assembly programming on OS level and this makes a huge difference.
Yes, Intel has managed to pack 102 million transistors per mm^2 (at "10nm") for Cannon Lake and Ice Lake. If I recall correctly TSMC and Samsung's "10nm" must be at around 45 to 55 million transistors per mm^2 (an estimate, since they do not report transistor densities). Better than Intel's "14nm" but way less dense than Intel's "10nm". Intel took a bigger leap in transistor density at "10nm", so the others will find it very hard to even match at it their "7nm". I doubt they will be able to go beyond 90 million transistors per mm^2, maybe 95 million tops. Which is why they avoid reporting transistor densities.
We know that despite using less dense processes, 14nm chips from Apple and AMD have much higher transistor densities than Intel 14nm. So even if Intel 14nm is denser in theory, that doesn't turn out to be the case in actual chips.
For the next generation of processes, TSMC 7nm has 117 million transistors per mm^2, Samsung 127, so their theoretical density is better than Intel 10nm at 103 million. Actual chips would likely show a far larger density advantage like on 14nm.
These are not the numbers I heard - I heard under 100 for either Samsung or TSMC
"We know that despite using less dense processes, 14nm chips from Apple and AMD have much higher transistor densities than Intel 14nm"
You lost all credit with this statement - possibly Apple - but no way AMD. From everything I seen from AMD they must double up or quad up CPU cores in a die to make it there. Also for AVX-256 they use double on 128 bit vectors
By the way Ice Lake is likely be much denser than Canon Lake.
Seriously why are you denying reality? There have been multiple articles comparing density, including recently on here about AMD vs Intel SRAM density. There was even a marketing response by Intel trying to explain away why Apple chips had higher transistor density.
> By the way Ice Lake is likely be much denser than Canon Lake.
That's simply your wish. In reality the 14+/++ process are significantly less dense than 14nm since the CPP has been relaxed to 84nm - that's a loss of 20% in density right there.
Exactly they will never reported transistor density. Because it they can use nm rating to say in theory they are twice as dense as 14nm. Ice Lake is a 10nm+ and is suppose to have significant improvements over Cannon Lake.
I am actually a little confused about the latest article about Cannon Lake - I heard it only going to be for Ultra Mobile laptops and tablets. But some information like AVX512 means that this chips is going to be extremely denser then current processors. Just a guess.
BTW I serious doubt if the 10nm version from TSMC and Samsung are 45 to 55 million, I serious doubt 7nm will even be 90 to 95, more likely would be 70 million.
Estimates put TSMC 7nm at 116 mT/mm^2, SS 7nm at 127 mT/mm^2.
I can understand not wanting to report transistor densities when your competitor who suddenly wants to use them has cherrypicked the reporting methodology.
Doesn't matter anyway, firstly availability matters: both TSMCs and SS's 10nm are working, mass production processes, and Intel's ... well, where is it? And secondly, it's what you do with it that counts.
REP MOV has been a ridiculously slow instruction since the early days of x86, and it still has a huge penalty on the latest implementations. GLIBC contains the fastest memcpy implementations - none of them uses REP MOV, so that says it all. Even if the penalty is smaller, REP MOV is never going to be fast.
Yes I've read the article and nothing in it indicates there will be a major speedup. All we know is Ice Lake will reduce the micro code penalty. Given REP MOV is practically never used precisely because it is so slow, it can't give a major speedup in existing code.
"Given REP MOV is practically never used precisely because it is so slow, it can't give a major speedup in existing code."
Question have you ever program in assembly or look at code that compiler generates - especially with string moves - in my experience REP MOV is used a lot and all over the place - but yes it is older x86 instruction then some of newer extensions like AVX-512. But keep in mind there is a lot of versions of REP MOV based on size of operand.
But it appears Intel is aware of the slowness and importance of this instruction
Keep in mind I have not used Intel assembly programing for about 25 years and a lot of advancements have happen since. But I am still knowledgeable about CPU design but not as much when I was doing OS development. Just the need for ASM developers is pretty much gone away. In fact back 1992, I did interview with Intel and they actually did not need ASM developers.
Why is "how many transistors can be pack[ed] in [the] same area" an important metric? Sure that might matter if you want you want to produce is a slab of SRAM, but most people demand more than that from their SoCs...
I obviously have no idea exactly what will be in, say, Canon Lake or Ice Lake, but if Intel is covering their SoCs just with SRAM caches because they can't think of anything more to add, while Apple (and others like Huawei) are adding LOGIC rather than caches (so ever more sophisticated GPUs, ISPs, and now NPUs) then it's not really of much interest to say that Intel has higher transistor density. Yeah, so what? All that's telling us is that Intel is putting vastly more "easy" transistors on their chips while the competition is putting many more "hard"(ie much more varied, much more random wiring) transistors on their chips.
Depends on how you compare it. If you compare Samsung 14nm LPP to Intel Intel definitely is better. If you're talking about 10nm I'm really not too sure, and if it's their 8nm vs. Intel 14nm if I had to guess I'd say Samsung is better.
Define "superior". If you mean "transistor density" Intel has clearly the best at every respective xxnm node, which is why they proposed to switch to transistor density in order to compare processes, rather than quote useless xxnm numbers. Transistor density (of the FEOL stack) is simple, clear, unambiguous and independently verifiable, so the company with the highest one can rise on top. So why do you think the other companies avoid it like a plague? I am sure you can hazard a guess.
Here is a slide by Intel comparing transistor density of several Apple chips with Broadwell and Skylake. The part on the left is the real transistor density (so literally #transistors / die size), the part on the right is mostly marketing.
Umm, do you know what the word density means? I don't want to mock you bcs English may not be your first language, but "transistor density" means "transistors per mm^2".
There is no such thing as "transistor density per mm^2".
However as the article explains, there is no single metric that can fully describe each node so they can be compared. Even if transistors had identical dimensions between 2 processes, there would be major differences in libraries, design rules, metal layers, performance, power, yield, cost, volume etc etc.
Did it ever occur to you that no such metric exists? One process may be superior for performance, another superior for power, another superior for cost, another superior for density?
You're asking something like "give me ONE number to show what's the best car".
"The 8LPP fabrication technology is an evolution of Samsung’s 10 nm node that uses narrower metal pitches and promises a 10% area reduction"
Samsung's shenanigans again. If area reduction is only 10%, then linear reduction is ~5%, so compared to 10nm it should be named 9.5nm process. :) Of course "10nm" is not 10nm to begin with. It is all still closer to 20nm as related to 45nm processes when things still used to be marked more or less honestly.
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34 Comments
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Kvaern1 - Thursday, October 19, 2017 - link
I wish you'd make a stand against ridiculous marketing department NM claims and instead use a useful metric to compare the processes.JoeyJoJo123 - Thursday, October 19, 2017 - link
>and instead use a useful metric to compare the processes.Like what?
Power, Performance, or Area Reduction of the new processes (discussed as such in the table in the article).
Kvaern1 - Friday, October 20, 2017 - link
I'm not qualified to decide what metric to use and I really don't care as long as the main ingredient isn't an arbitrary figure which came into existence in a marketing department meeting.peevee - Friday, October 20, 2017 - link
#transistors/sq mm.eek2121 - Thursday, October 19, 2017 - link
Half the people that discuss this do not know what they are talking about. I read a lot of people saying that 'only Intel' has a true 'XXnm node'. However, the only company to ever make that claim was Intel itself and it was not backed up by third parties. Furthermore, evidence suggests that Intel may have fabricated that statement. I'm willing to bet that Samsung process is far superior to Intel's at this current point in time.Wilco1 - Thursday, October 19, 2017 - link
For every process since 500nm the "true node" claim has been false - check the first graph in https://www.semiwiki.com/forum/content/6895-standa... The X in an X nm process is simply a label nowadays.Samsung 10nm is less dense than TSMC 10nm due to being earlier, and this should make it as good or better than TSMC 10nm. And yes, both are significantly better than Intel's current 14nm process. TSMC and Samsung 7nm are also better than Intel 10nm.
Gondalf - Thursday, October 19, 2017 - link
"TSMC and Samsung 7nm are also better than Intel 10nm"Strange claim, there is a good consensus between analists that Intel 10nm is pretty on line with TSMC 7nm.....Samsung 7nm process is pretty unknown right now.
Have you some informations that professional analists don't have??
Wilco1 - Thursday, October 19, 2017 - link
Bottom table in https://www.semiwiki.com/forum/content/6713-14nm-1...Gondalf - Friday, October 20, 2017 - link
You know what is Semiwiki (TSMC money sposorized from years, zero credibility).A good bunch of analists is far better. Try again my friend.
Wilco1 - Friday, October 20, 2017 - link
Ah I see, the published numbers don't agree with your bias, so they must be fake...HStewart - Thursday, October 19, 2017 - link
"TSMC and Samsung 7nm are also better than Intel 10nm"Personally I think this naming of 10nm vs 7nm process today reminds me the frequency wars in the past but in opposite direction. I believe the real thing is how many transistors can be pack in same area. From specs what I hear about what is coming in Cannon Lake and such and other slide I seen on Intel's process - I think we probably find that Intel's process is totally going to surprise people especially Samsung and TSMC.
But truthfully, it any ones guess until Intel releases - the news today about Icy Lake look very promising - especially in technical specs. I really love the faster REP MOV - if done right ( backward application compatible ) this could be a serious game change - I done almost 7 years straight of assembly programming on OS level and this makes a huge difference.
Santoval - Thursday, October 19, 2017 - link
Yes, Intel has managed to pack 102 million transistors per mm^2 (at "10nm") for Cannon Lake and Ice Lake. If I recall correctly TSMC and Samsung's "10nm" must be at around 45 to 55 million transistors per mm^2 (an estimate, since they do not report transistor densities). Better than Intel's "14nm" but way less dense than Intel's "10nm". Intel took a bigger leap in transistor density at "10nm", so the others will find it very hard to even match at it their "7nm". I doubt they will be able to go beyond 90 million transistors per mm^2, maybe 95 million tops. Which is why they avoid reporting transistor densities.Wilco1 - Thursday, October 19, 2017 - link
We know that despite using less dense processes, 14nm chips from Apple and AMD have much higher transistor densities than Intel 14nm. So even if Intel 14nm is denser in theory, that doesn't turn out to be the case in actual chips.For the next generation of processes, TSMC 7nm has 117 million transistors per mm^2, Samsung 127, so their theoretical density is better than Intel 10nm at 103 million. Actual chips would likely show a far larger density advantage like on 14nm.
HStewart - Thursday, October 19, 2017 - link
These are not the numbers I heard - I heard under 100 for either Samsung or TSMC"We know that despite using less dense processes, 14nm chips from Apple and AMD have much higher transistor densities than Intel 14nm"
You lost all credit with this statement - possibly Apple - but no way AMD. From everything I seen from AMD they must double up or quad up CPU cores in a die to make it there. Also for AVX-256 they use double on 128 bit vectors
By the way Ice Lake is likely be much denser than Canon Lake.
Wilco1 - Friday, October 20, 2017 - link
Seriously why are you denying reality? There have been multiple articles comparing density, including recently on here about AMD vs Intel SRAM density. There was even a marketing response by Intel trying to explain away why Apple chips had higher transistor density.> By the way Ice Lake is likely be much denser than Canon Lake.
That's simply your wish. In reality the 14+/++ process are significantly less dense than 14nm since the CPP has been relaxed to 84nm - that's a loss of 20% in density right there.
melgross - Friday, October 20, 2017 - link
We know that? Can you site some credible source for that?HStewart - Thursday, October 19, 2017 - link
Exactly they will never reported transistor density. Because it they can use nm rating to say in theory they are twice as dense as 14nm. Ice Lake is a 10nm+ and is suppose to have significant improvements over Cannon Lake.I am actually a little confused about the latest article about Cannon Lake - I heard it only going to be for Ultra Mobile laptops and tablets. But some information like AVX512 means that this chips is going to be extremely denser then current processors. Just a guess.
BTW I serious doubt if the 10nm version from TSMC and Samsung are 45 to 55 million, I serious doubt 7nm will even be 90 to 95, more likely would be 70 million.
Wilco1 - Friday, October 20, 2017 - link
Apple A11 has 48 million transistors per mm^2 (4.3B in 89 mm^2). What is there to doubt?Note TSMC 7nm transistor density improves not just by CPP and MMP scaling but gets an extra 25% via track scaling as well.
psychobriggsy - Tuesday, October 24, 2017 - link
Estimates put TSMC 7nm at 116 mT/mm^2, SS 7nm at 127 mT/mm^2.I can understand not wanting to report transistor densities when your competitor who suddenly wants to use them has cherrypicked the reporting methodology.
Doesn't matter anyway, firstly availability matters: both TSMCs and SS's 10nm are working, mass production processes, and Intel's ... well, where is it? And secondly, it's what you do with it that counts.
Wilco1 - Thursday, October 19, 2017 - link
This has realistic estimates for transistor density for Intel 10nm vs TSMC/Samsung 7nm based on published details: https://www.semiwiki.com/forum/content/6713-14nm-1... - nothing surprising.REP MOV has been a ridiculously slow instruction since the early days of x86, and it still has a huge penalty on the latest implementations. GLIBC contains the fastest memcpy implementations - none of them uses REP MOV, so that says it all. Even if the penalty is smaller, REP MOV is never going to be fast.
HStewart - Thursday, October 19, 2017 - link
Please look at the following Article from Amandtechhttps://www.anandtech.com/show/11928/intels-docume...
This is for Ice Lake - and if Intel does a significant speed up - it will be a game changer.
Wilco1 - Friday, October 20, 2017 - link
Yes I've read the article and nothing in it indicates there will be a major speedup. All we know is Ice Lake will reduce the micro code penalty. Given REP MOV is practically never used precisely because it is so slow, it can't give a major speedup in existing code.HStewart - Friday, October 20, 2017 - link
"Given REP MOV is practically never used precisely because it is so slow, it can't give a major speedup in existing code."Question have you ever program in assembly or look at code that compiler generates - especially with string moves - in my experience REP MOV is used a lot and all over the place - but yes it is older x86 instruction then some of newer extensions like AVX-512. But keep in mind there is a lot of versions of REP MOV based on size of operand.
But it appears Intel is aware of the slowness and importance of this instruction
https://software.intel.com/en-us/forums/intel-visu...
Keep in mind I have not used Intel assembly programing for about 25 years and a lot of advancements have happen since. But I am still knowledgeable about CPU design but not as much when I was doing OS development. Just the need for ASM developers is pretty much gone away. In fact back 1992, I did interview with Intel and they actually did not need ASM developers.
name99 - Friday, October 20, 2017 - link
Why is "how many transistors can be pack[ed] in [the] same area" an important metric?Sure that might matter if you want you want to produce is a slab of SRAM, but most people demand more than that from their SoCs...
I obviously have no idea exactly what will be in, say, Canon Lake or Ice Lake, but if Intel is covering their SoCs just with SRAM caches because they can't think of anything more to add, while Apple (and others like Huawei) are adding LOGIC rather than caches (so ever more sophisticated GPUs, ISPs, and now NPUs) then it's not really of much interest to say that Intel has higher transistor density. Yeah, so what? All that's telling us is that Intel is putting vastly more "easy" transistors on their chips while the competition is putting many more "hard"(ie much more varied, much more random wiring) transistors on their chips.
Dr. Swag - Thursday, October 19, 2017 - link
Depends on how you compare it. If you compare Samsung 14nm LPP to Intel Intel definitely is better. If you're talking about 10nm I'm really not too sure, and if it's their 8nm vs. Intel 14nm if I had to guess I'd say Samsung is better.Santoval - Thursday, October 19, 2017 - link
Define "superior". If you mean "transistor density" Intel has clearly the best at every respective xxnm node, which is why they proposed to switch to transistor density in order to compare processes, rather than quote useless xxnm numbers. Transistor density (of the FEOL stack) is simple, clear, unambiguous and independently verifiable, so the company with the highest one can rise on top.So why do you think the other companies avoid it like a plague? I am sure you can hazard a guess.
Wilco1 - Thursday, October 19, 2017 - link
Avoid it? The CPP/MMP/track/SRAM details have all been published. See https://www.semiwiki.com/forum/content/6713-14nm-1...Santoval - Thursday, October 19, 2017 - link
p.s. Not simply transistor density but "transistor density per mm^2", in order to normalize smaller and larger dies.Wilco1 - Friday, October 20, 2017 - link
Here is a slide by Intel comparing transistor density of several Apple chips with Broadwell and Skylake. The part on the left is the real transistor density (so literally #transistors / die size), the part on the right is mostly marketing.http://cdn.wccftech.com/wp-content/uploads/2016/09...
name99 - Friday, October 20, 2017 - link
Umm, do you know what the word density means?I don't want to mock you bcs English may not be your first language, but
"transistor density" means "transistors per mm^2".
There is no such thing as "transistor density per mm^2".
Wilco1 - Thursday, October 19, 2017 - link
A "standard node" metric has been proposed, see last graph in https://www.semiwiki.com/forum/content/6895-standa...However as the article explains, there is no single metric that can fully describe each node so they can be compared. Even if transistors had identical dimensions between 2 processes, there would be major differences in libraries, design rules, metal layers, performance, power, yield, cost, volume etc etc.
name99 - Friday, October 20, 2017 - link
Did it ever occur to you that no such metric exists?One process may be superior for performance, another superior for power, another superior for cost, another superior for density?
You're asking something like "give me ONE number to show what's the best car".
HollyDOL - Thursday, October 19, 2017 - link
And they claim 'size doesn't matter' :ppeevee - Friday, October 20, 2017 - link
"The 8LPP fabrication technology is an evolution of Samsung’s 10 nm node that uses narrower metal pitches and promises a 10% area reduction"Samsung's shenanigans again. If area reduction is only 10%, then linear reduction is ~5%, so compared to 10nm it should be named 9.5nm process. :) Of course "10nm" is not 10nm to begin with. It is all still closer to 20nm as related to 45nm processes when things still used to be marked more or less honestly.